LS842 TO-71 6L

LS840 LS841 LS842 LOW NOISE LOW DRIFT LOW CAPACITANCE MONOLITHIC DUAL N-CHANNEL JFET AMPLIFIER Over Three Decades of Quality Through Innovation FEATURES LOW NOISE en=8nV/Hz TYP. LOW LEAKAGE IG=10pA TYP. LOW DRIFT I VGS1-2/TI=5µV/ºC max. LOW OFFSET VOLTAGE ABSOLUTE MAXIMUM IVGS1-2I=2mV TYP. SOIC TO-71 & TO-78 TOP VIEW TOP VIEW RATINGS1 @ 25°C (unless otherwise noted) Maximum Temperatures Storage Temperature -55°C to +150°C Operating Junction Temperature -55°C to +150°C Maximum Voltage and Current for Each Transistor1 -VGSS Gate Voltage to Drain or Source 60V IG(f) Gate Forward Current 10mA Maximum Power Dissipation Device Dissipation2 @ Free Air - Total 400mW TA=+25°C ELECTRICAL CHARACTERISTICS @ 25ºC (unless otherwise noted) SYMBOL CHARACTERISTIC I VGS1-2 / TI max. Drift vs. Temperature LS840 LS841 LS842 UNITS 5 10 40 µV/ºC CONDITIONS VDG = 20V ID = 200µA TA = -55ºC to +125ºC IVGS1-2I max. Offset Voltage 5 10 25 mA SYMBOL VDG = 20V ID = 200µA CHARACTERISTIC3 MIN. TYP. MAX. UNITS BVGSS Breakdown Voltage -60 -- -- V VDS= 0 BVGGO Gate-to-Gate Breakdown ±60 -- -- V IGGO= ±1µA ID= 0 IS = 0 f = 1kHz CONDITIONS ID= -1nA TRANSCONDUCTANCE Gfss Full Conduction 1000 4000 µS VDG= 20V VGS= 0 Gfs Gfs1 Gfs2 Typical Conduction Transconductance Ratio DRAIN CURRENT 500 1000 µS VDG= 20V ID= 200µA 0.97 1.0 VDG= 20V ID= 200µA; Note 4 IDSS IDSS1 IDSS2 Full Conduction 0.5 mA VDG= 20V VGS= 0 Drain Current Ratio 0.95 2 5 1.0 GATE-SOURCE VGS(off) Pinchoff Voltage -1 -2 -4.5 V VDS= 20V ID= 1nA VGS Operating Range -0.5 -- -4 V VDS= 20V ID= 200µA GATE CURRENT -IG Operating -- 10 50 pA VDG= 20V ID =200µA -IG High Temperature -- -- 50 nA VDG= 20V ID =200µA TA=+125ºC -IG Reduced VDG -- 5 -- pA VDG= 10V ID =200µA -IGSS At Full Conduction -- -- 100 pA VDG= 20V VDS =0 Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201143 04/21/2016 Rev#A9 ECN# LS840 LS841 LS842 SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS CONDITIONS -- 10 µS VDG= 20V VGS= 0 VDG= 20V ID= 200µA OUTPUT CONDUCTANCE GOSS Full Conduction -- GOS Operating -- 0.1 1 µS │GOS 1-2│ Differential -- 0.01 0.1 µS -- 100 -- dB V DS= 10 to 20V ID=200µA -- 75 -- dB V DS= 5 to 10V ID=200µA VDS= 20V VGS= 0 f= 100Hz NBW= 6Hz VDS= 20V ID= 200µA f= 1KHz COMMON MODE REJECTION CMRR CMRR -20 log │V GS1-2/ V DS│ NOISE NF Figure -- -- 0.5 dB en Voltage -- -- 10 nV/Hz RG=10M NBW= 1Hz en Voltage -- -- 15 nV/Hz VDS= 20V ID= 200µA f= 10Hz NBW= 1Hz CAPACITANCE CISS Input -- 4 10 pF CRSS Reverse Transfer -- 1.2 5 pF CDD Drain-to-Drain -- 0.1 -- pF TO-71 VDS= 20V ID=200µA VDG= 20V ID= 200µA P-DIP TO-78 0.210 0.170 SOIC Note: All Dimensions in inches NOTES: 1. 2. 3. 4. These ratings are limiting values above which the serviceability of any semiconductor may be impaired Derate 4mW/ºC above 25ºC All MIN/TYP/MAX limits are absolute numbers. Negative signs indicate electrical polarity only. Assumes smaller number in the numerator. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems (LIS), established in 1987, is a third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company Founder John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, Co-Founder and Vice President of R&D at Intersil, and Founder/President of Micro Power Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201143 04/21/2016 Rev#A9 ECN# LS840 LS841 LS842